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SRF2003 Show Abstract

Title A new Digital Control System for CESR-c and the Cornell ERL
Type Poster coupler / tuner / controls
Abstract The present CESR RF control design is based on classic analog amplitude and phase feedback loops. In order to address the required flexibility of the RF control system in the CESR-c upgrade and to implement a true vector sum control we have designed, built and tested a new digital control system. The main features of the new controller are high sampling rates, high computation power and very low latency. The digital control hardware consists of a powerful VME processing board with a Xilinx FPGA, an Analog Devices digital signal processor (DSP) and memory. The Xilinx FPGA is used to compute the fast controller, while the floating-point DSP is used for higher level functions. A daughter board is equipped with four fast analog-to-digital converters (up to 65 MHz sampling rate) and two digital-to-analog converters (up to 50 MHz update rate). The first set of new electronics will be used in the CESR RF system. However, it can also be used for the proposed Cornell energy-recovery linac (ERL) as it was designed to meet the challenging ERL field stability requirements. In this paper we describe the layout of the new RF controller and present the results of initial performance tests.

List of authors...

Principle author first.

Last (Family) Name First Name (Initials only) Affiliation or Organization (abbreviations if possible)
Liepe M. Cornell University
Belomestnykh S. Cornell University
Dobbins J. Cornell University
Kaplan R. Cornell University
Strohman C. Cornell University

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